Calculating machines with control circuits to enter first number

ABSTRACT

An electronic calculating machine having a plurality of registers for containing numbers is disclosed, having an input register and an enter key for entering a first number into the input register and initiating an operation of corresponding control circuits, including the clearing of a register defined by a previous program adding this number in an accumulator register and entering the sum to both the input register and accumulator register.

United States Patent Inventors Appl. No. Filed Patented Assignee Priority CALCULATING MACHINES WITH CONTROL CIRCUITS TO ENTER FIRST NUMBER 9 Claims, 14 Drawing Figs.

US. Cl 235/168, 235/159,235/160 Int. Cl G061 7/385 Field of Search 235/159, 160, 168

References Cited UNITED STATES PATENTS 3,280,315 10/1966 Kitz 235/160 3,308,280 3/1967 Crowther et a1. 235/160 3,3 30,946 7/1967 Scuitto 235/160 3,358,125 12/1967 Rinaldi 235/160 X 3,375,356 3/1968 Scuitto 235/159 X 3,391,391 7/1968 Simpson 235/159 X 3,513,303 5/1970 Kitz Primary Examiner-Charles E. Atkinson Attorney--Laurence R. Brown ABSTRACT: An electronic calculating machine having a plurality of registers for containing numbers is disclosed, having an input register and an enter key for entering a first number into the input register and initiating an operation of corresponding control circuits, including the clearing of a register defined by a previous program adding this number in an accumulator register and entering the sum to both the input register and accumulator register.

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PATENTEDum- 12 Ian SHEET 11 0F 12 PATENTEDum- 12 Ian 3 6 1 2 846 SHEET 12 0F 12 |Il||||li||l|||!|l|llllillillllJ 9B 83 3 m u TL $3 r w% E NW NW Q9 F IIH I I l l l I I l IF L 3% 2 3 T I l l I l l l l l I l l I l l I l i l J u Q Q 5 E Q m 3 3 S a a a NW NW v Filllillltllillll llllllll IIIL ti S c CALCULATING MACHINES WITII CONTROL CIRCUITS TO ENTER FIRST NUMBER This invention has reference to calculating machines and more especially calculating machines embodying keyboards. Such keyboards are usually of the full keyboard type which embody a plurality of orders of keys or are of the single order type which include only a single set of keys representing the numbers -9. An example of a calculating machine embodying a full keyboard is described for example in out British Pat. No. 868753 an example of the single order type keyboard is described in Specification of our copending British application for Pat. No. 42/1966.

Such single order keyboard calculating machine embodies in addition to the keys representing the numbers 0-9 a series of keys which control the operation of the machine. For example there may be keys which control the operations of addition, subtraction, multiplication and division. As machines become more complex it is required that these keys control a larger number of operations and it is desirable to control as many operations as possible with a minimum number of control keys.

It is, therefore, an object of the present invention to provide an improved calculating machine.

It is a further object of the present invention to provide a calculating machine in which the number of operational keys is reduced.

According to one aspect of the present invention a calculating machine comprises an input register, an accumulator register, means for transferring numbers from the input register to the accumulator register and an operation key, selection of which causes the number entered in the input register to be transferred into the accumulator register nondestructively.

According to another aspect of the present invention a calculating machine includes an input register and an accumulator register, each register having a plurality of digit stages, a means for clearing the input register, a means for clearing the accumulator register, a means for controlling the operation of one of the register clearing means selected according to the previous program operation, an enter function key switch for initiating the operation of the control means, a means for adding the number in the input register to the number in the accumulator register and the accumulator register; whereby when the enter key switch is operated, the control means controls the operation of one of the register clearing means selected according to the previous program operation, the number in the cleared register is added to the number in the noncleared register and the sum number is entered into the input register and the accumulator register.

A constructional embodiment made in accordance with the invention will now be described, by way of example with reference to the accompanying drawings wherein:

FIGS. 1 and la show a block diagram of part of an electronic calculating machine made according to the invention;

FIG. 2 shows part of the set of gates 48 shown in FIG. 1 in greater detail;

FIG. 3 shows part of the set of gates 34 shown in FIG. greater detail;

FIG. 4 shows part of the set of gates 58 shown in FIG. greater detail;

FIG. 5 shows part of the set of gates 22 shown in FIG. greater detail;

FIG. 6 shows part of the set of gates 50 shown in FIG. greater detail;

FIG. 7 shows part of the set of gates 36 shown in FIG. greater detail; a

FIG. 8 shows part of the set of gates 76 shown in FIG. greater detail;

FIG. 9 shows part of the set of gates 72 shown in FIG. greater detail;

FIG. 10 shows part of the set of gates 11 shown in FIG. greater detail;

FIG. 11 shows part of the set of gates 54 shown in FIG. greater detail;

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FIG. 12 shows part of the set of gates 68 shown in FIG. 1 in greater detail; and

FIG. 13 shows part of the set of gates shown in FIG. 1 in greater detail.

The FIG. 1 shows an electronic calculating machine made according to the present invention. In FIG. 1 a master oscillator I generates free-running oscillator pulses GD which are on at +12 v. and off at 0 v. The oscillator l is connected to an input decade 2 which is connected as a Johnson ring circuit. The input decade 2 divides the master oscillator pulses GD into sequential groups of 10 pulses, viz. P0, P1, P2, P3, P4, P5, P6, P7, P8 and P9.

The output pulses P0 to P9 from the input decade 2 are internally gated to give waveforms P0, P5 and P9, a waveform 9, and a waveform a'P9.

Waveform P0" is up (at +12 volt) from the back edge of the P9 pulse to the back edge of the P0 pulse.

Waveform P5 is up from the back edge of P4 pulses to the back edge of P5 pulse.

Waveform P9 is up from the back edge of P8 pulse to the back edge of P9 pulse.

Waveform 9 is up from the back edge of P0 pulse to the back edge of P9 pulse.

Waveform dP9" is up from the back edge of P9 pulse to the front edge of P0 pulse.

The calculating machine has a digit keyboard 5 having 10 normally open digit key switches (not shown) representing the digits 0-9 respectively, which switches are closed when the corresponding keys (not shown) are depressed.

The normally open contact of the digit key switches (not shown) representing the digits 0-9 respectively are connected to the pulses P9 to P0 respectively and the connections to the movable contact of the digit key switches are connected to a gate circuit 7 which has an output to a highway HW2. When a digit key (not shown) is depressed to close the corresponding digit key switch, a train of pulses of number equal to the digit corresponding to the digit key depressed, is repetitively transmitted along the highway I-IW2 until the depressed digit key is released.

The calculating machine also has a function keyboard 8 which has function key switches (not shown) marked with the following symbols and the key switches 80, 8b and So which are marked decimal point, constant, and enter" respectively. The function key switches (not shown) marked X, and which control the arithmetical functions of addition, subtraction, multiplication and division respectively, are similar to the digit key switches and are connected in a similar way to a gate circuit 9. The output from the gate circuit 9 is connected to a highway HW3. The key switches 8a, 8b, and 8c are normally open and are connected to a source of positive potential so that when the key is depressed a signal is transmitted along the corresponding line. When a function key is closed by depression of the function key, the corresponding function signal is transmitted along the highway HW3. The four function signals transmitted along highway I-IW3 are:

on depression of the key, up at the back edge of P7, down at the back edge of P0;

on depression of the key, up at the back edge of P7, down at the back edge of P0;

on depression of the X key, up at the back edge of P3, down at the back edge of P0;

on depression of the key, up at the back edge of P5, down at the back edge of P0.

The entry key transmits a CE signal along the line C.E., when the entry key is depressed. The decimal point key transmits a DP" signal along the line D.P., when'the decimal point key is depressed; and the constant transmits a constant signal 'rr along the line 1r, when the constant key is depressed.

A function counter circuit 10, which is a decade counter internally interconnected to have eight count stages, has seven of the outputs labeled in order of ascending count state the function positions F0, F1, F2, F3, F4, F5, F6, F7 respectively.

The eight count output, which is labeled the function position dF0, comes up at the back edge of the function position, F and goes down approximately 0.5 in sec. later. The input of the function counter circuit 10 is connected by a highway HW4 to a set of gates 11. The function counter outputs of function positions are connected to, and control the operation of, logic gates as hereinafter described. The function counter circuit 10 waits at F0 and, when a function key is operated, the function counter circuit is driven by the pulses transmitted along highway I-IW4 to the corresponding function position which activates those logic gates which are used to perform the corresponding function. When the function is completed, a stop gate (not shown) drives the output 'of the function counter circuit 10 back to F0. The functions controlled by the function position are:

F0 display or wait F4 subtract Fl clear F5 divide F2 index F6 spare F3 add F7 multiply A timer circuit 12, which is a 7-position Johnson ring circuit is internally interconnected to have 13 count stages which are labeled in order of ascending count states TO TD, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11. The timer circuit 12 is driven continuously by P9 pulses from the input decade 2 so that the count state outputs are sequentially and continuously generated and each count state output lasts from the back of the P9 to the back edge of the next P9 pulse.

A visual display 14 includes ID number tube circuits each having a number tube 16 and decimal point neon bulbs 17. The anodes of number tubes 16 are connected in sequence to a positive potential under the control of the outputs T1 to T10 respectively of the timer circuit 12. The highest significant digit in a displayed number is positioned in the left hand number tube, which is controlled by the output T10, by means of circuits hereinafter described.

One connection to each of the neon bulbs 17 is connected together and these are connected to the output TD of the timer circuit 12. The cathodes of the 10 number tubes 16 which are shaped to the same digit are connected together. The other connection of the neon bulb 17 at the left-hand side of FIG. I is connected to the bunched cathode connections showing the digit 0; the other connection of the next neon bulb being connected to the bunched cathode connections showing the digit 1; and so on until the other connection of the 10th neon bulb 17 is connected to the bunched cathode connections showing the digit 9.

The 10 bunched cathode connections are connected to the outputs of a row of bistables which form a staticiser 18. The inputs of the staticiser 18 are connected to the outputs of a storage means in the form of a bufi'er decade counter 20 which is internally interconnected so as to convert a train of pulses into the binary-coded decimal equivalent which appears, on the outputs of the decade counter. The input of the buffer 20 is connected by a highway HW8 to the output of a third set of gates 22, part of which is shown in FIG. 5. The contents of the buffer 20 are cleared from the buffer 20 into the staticiser 18 at the front edge of each P0 pulse and the staticiser 18 is cleared, i.e., the digit 0 line is energized, at the back edge of each P9 pulse. The buffer 20 has an output B0 which is energized, i.e. goes to a positive potential, when the buffer 20 stores a digit zero, so that the number cleared from the buffer 20 stays in the staticiser 28 for nearly the duration of an out put from the timer circuit 12. The buffer output B0 is connected to the invertor circuits 229a (FIG. 5) 513a (FIG 6) and 369a (FIG. 7) so that an inverted buffer output B0 is produced.

The number tube 16 connected to the output T2 of the timer circuit 12 displays the units digit, the number tube 16 connected to the output T3 displays the tens digit and so on.

The position of the decimal point is given by a train of pulses loaded into the buffer 20 when the output TD of the timer circuit 12 is energized and is entered into the staticiser l8 and is displayed by the neon bulb 17 at the position corresponding to the number of pulses in the train, when the next output T1 of the timer circuit is energized. Similarly, if, for example the digit 4 is to be displayed at the tens position, a train of four pulses is entered into the buffer 20 when the output T2 of the timer circuit is energized and the binary-coded decimal equivalent of the digit 4 appears on the output of the buffer 20. This binary-coded decimal output is transferred from the buffer 20 to the staticiser 18 at the pulse P0 and the digit 4 is displayed on that number tube 16 which is switched on when the output T3 of the timer circuit 12 is energized. The digit 4 is cleared from the staticiser 18 when the pulse P9 occurs at the end of the time in which the output T3 is energized. The frequency at which the outputs from the timer circuit 12 are energized are such that the digits appearing on the number tubes 16 and the decimal point appearing on a neon bulb 17 appear to be stationary because of the persistance effect of ocular vision.

A second or input register 24 has four shift registers 25a, 25b, 25c and 25d each having 12 digit stages. The input and output of the four shift register 25a, 25b and 25d are each connected in a loop with a shift register buffer 26 in the form of four bistable circuits which are internally interconnected to form a decade counter and which act as the l3th digit stage. The shift pulse input to four shift registers 25a, 25b, 25c and 25d and the shift register buffer 26 are connected by a highway HWlS to a set of gates 34 part of which is hereinafter described (FIG. 3). The set of gates 34 provide shift pulses dP9 to the four shift registers 25a, 25b, 25c and 25d and to the shift register buffer 26 so that the binary-coded decimal digits in the four shift registers circulate through the shift register buffer 26 and back to the input of the shift registers respectively.

A carry pulse output of a bistable circuit of the shift register buffer 26, which output is energized when the digit in the shift register buffer 26 goes from the count of nine to the count of zero, is connected to the input of a carry store 28. The carry store 28 comprises a first bistable circuit 30 having the outputs CO1 and GCTI and a second bistable circuit 32 having the output CPOl. The set connections from the first bistable circuit 30 and the second bistable circuit 32 respectively are connected to the carry pulse output of the shift register buffer 26. The first bistable circuit 30 is reset by a pulse P0 so that the output Gm is energized i.e., is at a positive potential. A carry pulse from the shift register buffer 26 causes the output CO] to be energized. The second bistable circuit 32 is reset by a pulse P5, so that the output CPOl is not energized until a carry pulse is received from the shift buffers. A fifth set of gates 36, partly hereinafter described (FIG. 7), are connected by a highway HWS to the input of the shift register buffer 26.

A first or accumulator register 38 has four l2-stage shift registers 39a, 39b, 39c and 39d, a shift register buffer 40 and a carry store 42 as previously described for input register 24. The shift pulse inputs of the four shift register 39a, 39b, 39c and 39d and the shift register buffer 40 are connected by a highway HW16 to a set of gates 48 partly hereinafter described (FIG. 2). The carry pulse output of the shift register buffer 40 is connected to the set input of the carry store 42 which corm ises a first bistable circuit 44 having the outputs CO2 and CO2 and a second bistable circuit 46 having an output CPO2. The fir st bistable circuit 44 is reset by a pulse P0 so that the output CO2 is energized and the second bistable circuit is reset by a pulse P5 so that the output CF02 is not energized. The shift register buffer 40 is connected by a highway l-IWl to a fourth set of gates 50, partly hereinafter described (FIG. 6).

Thus in the input register 24 and the accumulator register 38 the shift registers and the shift register buffers form 13 stage loops around which pulse patterns circulate in synchronism with the energized outputs of the timer circuit 12. If the input register 24 or accumulator register 38 receives thirteen shift pulses, the digit in the units or T1 digit stage of the input register 24 or accumulator register 38 is in the shift register buffer 26 or 40 respectively when the output T1 of the timer circuit 12 is energized. Similarly the tens or T2 digit stage of the input register 24 or accumulator register 38 is in the shift register buffer 26 or 40 respectively when the output of the timer circuit T2 is energized, and so on.

If one shift pulse to a register is supressed, so that the register only receives 12 pulses, the number in the register is moved one place to the left with respect to the outputs of the timer circuit I2.

If an extra shift pulse is gated into a register with the pulse PS, the number in the register is moved one place to the right with respect to the outputs of the timer circuit 12.

A slip counter 52, which is a 4-bistable ripple-through counter internally interconnected to have 13 count states which are labeled in ascending order of count state SO, SD, SI ...Sll has outputs connected to the S0 and S11 count states. The outputs to the count states SO and 811 are cortnectedlo invertor circuits (not shown) to give the outputs S0 and S11 respectively and S0. The outputs Sl'l, 8T1 and S0 are used to control logic circuit gates. The input of the slip counter 52 is connected by a highway I-IW6 to a second set of gates 54. The slip counter 52 is driven by P9 pulses to maintain its energized count states in correspondence with the energized count state outputs of the timer circuit 12. Shift pulses are suppressed or extra ones gated in through the set of gates 54 partly shown hereinafter (FIG. 11). The main purpose of the slip counter 52 is to keep a record of the amount of slip with respect to the timer circuit 12 which occurs when anumber is shifted in the input register 24 or the accumulator register 38.

A decimal counter 56, which is a 4-bistable ripple-through counter internally interconnected so as to have count states, has its output connected to the set input of an output bistable circuit 60. The input of the decimal counter 56 is connected by a highway HW9 to a set of gates 58, partly hereinafter described (F I G 4). The output bistable circuit 60 has the outputs D0 and DO. The output bistable circuit 60 is arranged so that the output D0 is energized when the count in the decade counter 56 goes to or passes through the zero count state; the output bistable circuit 60 is reset so that the output D 0 is energized by the next'P0 pulse.

The decimal counter 56 holds the count corresponding to the position of the decimal point digit of a number stored in the accumulator register 38. This decimal point digit is held separately from the other digits in the accumulator register 38 because the accumulator register is used for calculation of products and quotients and the whole accumulator register 38 is required for holding partial products or partial remainders during the calculation. The decimal point digit is also held separately because the answer in the accumulator register 38 may need to be repositioned so as to display the most significant digit of the answer in the left-hand number tube 16 of the visual display 14, and this is more easily done if the decimal point digit is held separately.

A bistable circuit 62 having the outputs A and A has the input connected by a highway I-IW13 toa set of gates 64. A bistable circuit 66 having the outputs C and C has the input connected by a highway HW7 to a. gt of gates 68. A bistable circuit 70 having the outputs D and D has the input connected by a highway HWll to a set of gates 72, partly hereinafter described (FIG. 9). A first bistable circuit 74 having the one and other outputs E and E respectively, has the input connected by a highway HW12 to a first set of gates 76, partly hereinafter described (FIG. 8). A bistable circuit 78 having the outputs H and H has the input connected by a highway HWl4 to a set of gates 80 partly hereinafter described (FIG. 13).

The bistable circuit 62 controls which register has its number displayed by the visual display 14. If the bistable circuit 62 is set so that the output A is energized the number stored in the input register 24 is displayed; if the bistable circuit 62 is set so that the output A is energized the number stored in the accumulator register 38 is displayed.

The second bistable circuit 66 having the outputs C and C controls the time at which the input register 24 can shift with respect to the accumulator register 38 so that the four arithmetic functions can be performed by the calculating machine. If the bistable circuit 66 is set so that the output C is energized shift can take place; if the bistable circuit 66 is reset so that the output C is energized the registers are held so that shift cannot take place.

The bistable circuit 70 together with the bistable circuit 66 controls the number of shift pulses sent through the set of gates 34 and 48 to the input register 24 and the accumulator register 38 respectively. The control operation is more fully described hereinafter.

The bistable circuit 74 has a control function as hereinafter described.

The FIGS. 2 to 13 show in greater detail, part of some of the set of gates shown in FIG. 1. Unless otherwise indicated in the description the circuits shown are "and" logic circuit gates.

The FIG. 2 shows in detail part of the set of gates 48 shown in FIG. 1. The set of gates 48 includes the and" gates 480, 482 and 487, a transistor invertor circuit 480a, a time delay circuit 482b, and a' circuit 486a. The circuit 486a comprises a transistor. invertor circuit 486b whose input is connected to the output D0 of the output bistable 60 and whose output is connected to an and" logic gate 4860. The output of the and gate 486:: is connected to a capacitor C and to a transistor invertor circuit 486d.

The FIG. 3 shows in detail part of the set of gates 34 shown in FIG. 1 The circuit in the Figure comprise the and" gates 340, 342, and 343, the or" gates 342a and 343a and a transistor invertor circuit 340a for the output T0 of the timer circuit 12.

The FIG. 4 shows in detail part of the set of gates 58 shown in FIG. 1. The circuits in the Figure comprise the and" gates 580, 581, 586 to 589 and 591, and the time delay circuits 589a and 591a.

The FIG. 5 shows in detail part of the third set of gates 22 shown in FIG. 1. The circuits in the Figure comprise the and gates 220, 221, 222, 228 and 229 and the invertor circuits 222a, 228a, 228b and 2290, for the outputs to and TD of the timer circuit 12, and B0.

The FIG. 6 shows in detail part of the set of gates 50 shown in FIG. 1. The circuits in the Figure comprise the and" gates 500 to 502, 511 to 513, and 517 to 521, transistor invertor circuits 500a, 500b, 513a, 513b, 517a, 519a, 519b, 5210, and 512b, a transistor invertor and" gate 512a, and a transistor invertor time delay circuit 520a.

The FIG. 7 shows in detail part of the set of gates 36 shown in FIG. 1. The circuits in the Figure comprise the and" gates, 360, 362, 363, 367 to 369, 371 and 373, the transistor invertor circuits 360a, 363a, 368a, 3690, 36% and 373a and a transistor invertor "and" gate 368b.

The FIG. 8 shows in detail part of the set of gates 76 shown in FIG. 1. The circuit shown in the Figure comprises the "and" gates 762 to 766 and a time delay circuit 766a.

The FIG. 9 shows in detail part of the set of gates 72 shown in FIG. 1. The circuits shown in the Figure compress the and" gates 720 and 723 and a transistor invertor or gate circuit 720a.

The FIG. 10 shows in detail part of the set of gates l 1 shown in FIG. 1. The circuit shown in the Figure comprises the and gates 110, 112, 114, 118 and 119, the transistor invertor circuit a and 118a a transistor invertor and or gate 110b, a %-second time delay circuit 110a and a IO-millisecond time delay circuit 114a.

The FIG. 11 shows in detail part of the set of gates 54 shown in FIG. 1. The circuit shown in the Figure comprises the and gates 540, 541, 545 to 547 and 549, the or' gates 545a, 546a and 547a and a transistor invertor circuit 547b.

The FIG. 12 shows in detail part of the set of gates 68 shown in FIG. 1 The circuit shown in the Figure comprises the and' gates 680 and 689.

The FIG. 13 shows in detail part of the set of gates 80 shown in FIG. 1. The circuit shown in the Figure comprises the and gates 801 and 802.

The gate 480 (FIG. 2) supplies l2 shift pulses 1122 and the gate 486 supplies the 13th shift pulse if the input LS is energized so that the shift pulses to the accumulator register 38 and the outputs of the timer circuit 12 occur in synchronism.

The calculating machine has other circuitry (not shown) which is interconnected with the parts of the calculating machine shown in the Figures so that numbers can be entered into the input register 24 and accumulator register 38 through the digit keyboard 5, which numbers are used to perform arithmetic calculations selected from those on the function keyboard 8.

The answer to a calculation is stored in and circulates around the accumulator register 38 and is displayed when the inputs marked F on the different gates are energized. A digit is shifted into the shift register buffer 40 of the accumulator register 38 by a dP9 pulse which occurs at the same time as the next output of the timer circuit 12 is energized. The gate 500 (FIG. 6) is energized for the outputs T1, Td and T2 to T10 of the timer circuit 12 and allows l0 oscillator GD pulses (corresponding to the pulses P0 to P9) to circulate the digit in the shift register buffer 40. At the same time the gate 222 FIG. is shut (since the first bistable circuit 44 was reset by the first pulse PO) and does not allow oscillator GD pulses to pass into the buffer 20. When the digit in the shift register buffer 40 goes through zero, a pulse is passed to the first bistable circuit 44 and the second bistable 46 so that the outputs C02 and CF02 are energized. When the input C02 is energized the gate 222 allows a number of oscillator pulses GD, which are equal to the digit in the shift register buffer 40, to enter the buffer 20. As previously described, the digit in the buffer 20 is cleared into the staticiser 18 at the next P0 pulse (which also resets the first bistable circuit 44) and the digit is displayed on the visual display 14.

An outline of the various sequences of internal operations initiated 'when the clear key is depressed at various stages during the operation of the calculating machine will now be given. A detailed description of these various sequences of internal operations will be given later.

The clear can be depressed at three places during the operation of the calculating machine. These places" are: (a) immediately after switch-on of the calculating machine, (b) after entry of a number into the calculating machine and (c) after the operation of a function key.

The effect of depressing the clear key immediately after switch-on is to initiate a program which sets certain counter circuits and bistable circuits to initial conditions and also initiates a program in which the number in the accumulator register 38 is cleared while the number in the input register 24 is not cleared but it circulated. The number in the input register 24 is then added to the cleared accumulator register 38 by an addition routine. The number in the accumulator register 38 is then copied back into the input register 24 by a copy routine so that the number originally in the input register 24 ends up in the input register 24 and the accumulator register 38.

The addition routine begins with a subroutine which comprises the subtraction of the decimal point count of the input register 24 from the decimal point count of the accumulator register 38 and then a relative shift between the input register and the accumulator register by a number of stage positions equal to the difference between the decimal point counts. The addition subroutine then follows with the answer stored in the accumulator register. The answer in the accumulator register 38 may be shifted within this register by circuits not described, so that the highest significant digit is displayed in the number tube 16 of the visual display 14 which is energized by the output T of the timer circuit 12.

The copy routine, which follows the addition routine, comprises a two-stage routine which is continuously repeated. When the copy routine is initiated, the first stage begins with the most significant digit of the number in the accumulator register 38 being transferred to the buffer 20. During the first stage the highest significant digit stages of the input register 24 and the accumulator register 38 are cleared. During the second stage the highest significant digit stored in the buffer 20 is transferred into the cleared highest significant digit stages of the input register 24 and the accumulator register 38. This two-stage sequence is repeated digit by digit until the number remaining in the accumulator register 38 after the addition routine has been copied into both the input register 24 and the accumulator register 28.

The effect of depressing the clear key after the entry of a number into the calculating machine is to cause the number which is entered in the input register 24 to be added into the cleared accumulator register 38 and then copied into the input register 24 and the accumulator register 38. The addition and copy routines are identical to those previously described.

The effect of depressing the clear key after the depression of the function key is to cause the zeros of the cleared input register 29 to be added to the number in the accumulator register 38. The unchanged number in the accumulator register 38 is then copied into the input register 24 and accumulator register 38. The addition and copy routines are identical to those previously described.

A detailed description of the operations previously outlined will now be given.

In the description, the stage of the input register 24 or the accumulator register 38 from which a digit is taken and loaded into the buffer 20 when an output of the timer circuit 12 is energized is for convenience labeled with that timer circuit output. For example, the digit stage of the input register 24 from which is taken the digit which is loaded into the buffer 20 when the timer circuit output TD is energized is called the TD stage of the input register 24. Also, in the description, a timing period means the time taken for the outputs TO, TD to T11 inclusive of the timer circuit 12 to be energized in sequence.

The calculating machine operates as follows:

When the calculating machine is switched on the gate clears the function counter circuit 10 to the output F0 after a delay of one-quarter of a second. At the end of this delay, other gates having the function counter output F0 as an input are in the enabled state. The gate 720 resets the bistable circuit 70 to energize the output D, The gate 500 circulates the number in the accumulator register 38 and the gate 501 clears the T1 1 stage of the accumulator register 38. The gate 580 circulates the decimal count stored in the decimal counter 56, when the output TD of the timer circuit 12 is energized. The gate 360 circulates the number in the input register 24. The gate 221 loads the buffer circuit 20 to display input register 24 or the gates 220 and 222 load the buffer circuit 20 to display the number stored in the accumulator register 38. The gate 501 clears the digit stage of the accumulator register 38 which is enabled by the energized T1 1 output of the timer circuit 12.

If the enter key on the function keyboard 8 is depressed immediately after switch-on the depression of the enter key causes the clear and enter signal C.E. to be energized i.e. to go from 0 volts to +12 volts. The gate 540 clears the slip counter 52 so that the count state S0 is energized. The gate 680 sets the bistable circuit 66 to energize the output C.

The gate 762 energizes the output E of the bistable circuit 74 if the output E was previously energized. The gate 114 pulses the function counter 10 so that the output F1 is energized. The gate 362 circulates the number stored in the input register 24, if the output A of the bistable circuit 62 is energized, and overrides the gate 363 which would otherwise clear the input register 24. The gate 502 clears the number in the accumulator register 38 and the gate 581 clears the accumulator decimal point count from the decimal counter 56. The gate 112 pulses the function counter 10 so that the output F2 is energized. The gate 541 causes the output of the slip counter 52 to move directly from S0 to S11. The gate 119 pulses the function counter 10 so that the output F3 is energized and the addition routine is initiated. The gate 801 ensures that the outputfi of the bistable circuit 78 is energized.

The addition routine begins with the following outputs energized: bistable circuits outputs A or A, C, D, E and ll; slip counter output S11; function counter output F3; timer circuit output T and input decade output P0.

The first subroutine of the addition routine is to align the numbers in input register 24 and the accumulator register 38 so that, in effect, the decimal point counts are the same. This alignment is done by subtracting the input register decimal point count from the accumulator register decimal point count stored in the decimal counter 56 by means of the gate 588. At the end of the subtraction subroutine, the output of the bistable circuit 60 which is energized depends on which register originally had the greater decimal point count. 1f the decimal point count of the accumulator register is greater than the decimal point counter of the input register (case 1), the energized output o f the output bistable circuit 60 is changed from the output D0 to the output D0 and a pulse count which is equal to the difference betweenthe decimal points is stored in the decimal counter56. If the decimal point count of the input register 24 is greater than the decimal point count of the accumulator register 38 (case 2), the energized out t of the output bistable circuit 60 remains unchanged to D0 and a count equal to the tens complement of the difference between the decimal points is stored in the decimal counter 56.

When the accumulator register decimal point count is greater than the input register decimal point count (case 1), each time the output TD of the time circuit 12 is energized the gate 765 sets the bistable circuit 74 so that the output E is energized and; because in this condition the output D0 is energized, the gate 766 resets the bistable circuit 74 so that the output E is energized. When the next timer output, the output T1, of the timer circuit 12 is energized, the p t i l se P0 sets the output bistable circuit 60 so that the output D0 is energized. During the next timing period of the timer circuit 12, during which the outputs T0 to T11 are sequentially energized; the gates 480 and 487 pass 13 shift pulses to the accumulator register 38 while the gates 340, 342 and 343 and the gates 545, 546 and 547 pass 14 shift pulses to the input register 24 and the slip counter 52 respectively so that the input register 24 moves one digit stage with respect to the accumulator register 38. During this timing period of the timer circuit 12 the gate 589 causes the nine pulses of the output 9' from the input decade 2 to circulate and reduce by one the count in the decimal counter 56. The timing periods of the timer circuit 12 and the operation of the gates previously described are repeated until the difference count in the decimal counter 56 is 0 so that the output D0 of the output bistable circuit 60 remains energized after the application of the reset pulse P0 occurring when the timer output T1 is energized. The second subroutine of the addition routine, the addition of the number in the input register 24 to the number in the accumulator register 38, follows and is described later.

When the input register decimal point count is greater than the accumulator register decimal point count (case 2), each time the output TD of the timer circuit 12 is energized the gate 765 sets the bistable circuit 74 so that the output is energized. During the next timing period of the timer circuit 12, during which the outputs T0 to T11 are sequentially energized, the gates 340 and 343 and the gates 546 and 547 pass 13 shift pulses to the input register 24 and the slip counter 52 respectively and the gates 480, 482 and 487 pass 14 shift pulses to accumulator register 38 so that the accumulator register 38 moves one digit stage with respect to the input register 24. During this timing period of the timer circuit 12 the gate 591 causes a pulse to increase by one the count in the decimal counter 56. The timing periods of the timer circuit 12 and the operation of the gates previously described are repeated until the count in the decimal counter 56 is 0 so that the output D0 of the output bistable circuit 60 remains energized after the application of the reset pulse P0 occurring when the timer output T1 is energized. The second subroutine of the addition routine, the addition of the number in the input register 24 to the number in the accumulator register 38, follows and is described later.

The second subroutine of the addition routine, the addition operation, begins when the output D0 of the output bistable circuit 60 remains energized after the application of the reset pulse P0 occurring when the timer output T1 is energized. The gates 373, 517 and 521 control the addition of the number in the input register 24 to the number in the accumulator register 38. At the end of the addition routine @e gate 723 pulses the bistable circuit 70 so that the output D is energized and the gate 689 pulses the bistable circuit 66 so that the output 6 is energized. The digit stage T11 of the accumulator register 38 is left in the cleared state at the end of the addition routine. If the accumulator T11 digit stage has a carry from the T10 digit stage, gate circuits (not shown) shift by one digit the number stored in the accumulator register so that the most significant digit of the number is shifted from the T11 digit stage to the T10 digit stage.

The subtraction routine is similar to the addition routine and uses the usual method of adding the nines complement of the number in the input register 24 plus one digit to the number in the accumulator register, using the gates 518,519 and 520 (FIG. 6). As the addition and subtraction routines are so similar, when the other function counter output F4 is energized, the one output F3 is also energized and any a ddition gates not required for subtraction are closed by a F4 signal from the outputof the invertor circuit 517a (FIG. 6) whose input is connected to the F4 output.

At the end of the second subroutine of the addition routine and the beginning'of the copy routine, the output T11 of the timer circuit 12 and the output 81] of the sli counter 52 are energized, together with the outputs C and of the bistable circuits 66 and 70 respectively. The gate 763 ensures that output E of the bistable circuit 74 is energized at the beginning of the copy routine and during the first timing period of the timer circuit 12. During the first timing period the gate 549 controls the transmission of one pulse to the slip counter 52 so that the gates 228, 367 and 511 are energized when the timer circuit output T10 coincides with the slip circuit output 811. The gate 228 and the gate 511 clear the T10 stage of the accumulator register 38 into the buffer 20. The gate 367 clears the T10 stage of the input register 24. At the end of the first timing eriod the gate 764 pulses the bistable circuit 74 so the output is energized. During the next timing period of the timer circuit 12 the gate 229 zeros the buffer while the gates 368 and 512 control the transmission of the contents of the buffer to the T10 stages of the input register 24 and the accumulator register 38 respectively. At the end of the second timing gate 764 pulses the bistable circuit 74 so that the output E is energized. At the beginning of the third timing period the gate 549 controls the transmission of one pulse to the slip counter 52 so that the gates 228, 367 and 511 are energized when the timer circuit output T9 coincides with the slip circuit output S11. The copy routine continues until the timer circuit output TD coincides with the slip counter output S11 so that the gate 586 adds the input register decimal point to the accumulator register decimal point while the output E of the bistable circuit 74 is energized. The gates 587 and 371 cause the accumulator decimal point to be circulated and copied into th e TD stage of the input register respectively, when the output E of the bistable circuit 74 is energized. When all of the numbers have been copied, the output B0 of the buffer 20 is energized at the same time as the timer circuit output T11 and the slip counter out put Sll, so that the gate 118 pulses the function counter 10 so that the output F0 is energized so that the copied number is displayed on the visual display 14.

if, as a result of the subtraction operation performed immediately before the copy routine, the answer to subtraction operation is negative, the subsequent copy routine is changed to a complement copy routine. If at the end of the subtraction operation, the answer is negative, the gate 802 pulses the bistable circuit 78 so that the output H is energized. The output H causes the gates 368 and 512 to be closed and the gates 369 and 513 to be opened so that the complement of the digit in the buffer 20 is transferred or copied to the input register 24 and the accumulator register 38 respectively, when the output E of the bistable 74 is energized. Thus the complement copy routine only differs from the ordinary or noncomplement copy -routine by the value of the digit transferred from the buffer 20 to the input register 24 and the accumulator register 38.

If the clear key on the function keyboard 8 is depressed after a number has been entered, or indexed, into the input register 24, an identical operation occurs to that previously described when the clear key is depressed after switch-on. Thus, the number originally entered into the input register 24 is copied into the input register 24 and the accumulator register 38.

If the clear key on the function keyboard 8 is depressed after an arithmetical operation has been completed, the input register 24 is cleared and the accumulator register 38 is not cleared, since the answer to the arithmetic operation is stored in the accumulator register, before the addition and copy routines previously described are performed. At the end of the arithmetic routine the output A of the bistable circuit 62 is energized so that the answer storedin the accumulator register 38 is displayed by the visual display 14. The effect of depressing the clear key causes the same sequential operation of the function counter outputs F0, F1, F2 and F3 as previously described. However, after the gate 114 pulses the function counter so that the output F1 is energized, the energized output A inhibits the gates 502 and 581 to prevent the accumulator register from being cleared. The energized output A also inhibits the gate 362, which prevents the input register 24 from being cleared, so that the gate 363 controls the clearing of the input register 24. The gate 112 pulses the function counter 10 so that the output F2 is energized and the subsequent operations are identical to those previously described.

The copy routine and the complement copy routine are not limited to use with theaddition and subtraction routines respectively described above. The copy routines can be arranged to be directly or indirectly initiated by any of the outputs of the function counter 10.

What we claim is:

l. A calculating machine having programmed operations includingan input register and an accumulator register, each register having a plurality of digit stages, a means. for clearing the input register, a means forclearing the accumulator register, clearing control means operable from the previous program operation for controlling the operation of a single one of the register clearing means, an enter function key switch for initiating the operationof the clearing means, a means for entering a number in the input register and a number in the accumulator register, means adding the number in the input register to the number in the accumulator register and a means for entering the sum number into both the input register and the accumulator register by means of the enter key switch so that the clearing control means controls the clearing of one of the registers selected according to the previous program operation, the number in the cleared register is added to the number in the noncleared register and the sum number is entered into both the input register and the accumulator register.

2. A calculating machine according to claim 1, including means to enter the sum number in the accumulator register into the input register.

3. A calculating machine according to claim 1 wherein the enter function key switch has means for establishing in one operating condition a signal at one voltage level along a line and for the other operating condition establishing a signal at another voltage level along the line; and wherein an inverter circuit is connected to the line to produce an inverted output.

4. A calculating machine according to claim 3 having control means including a master oscillator; and input decade having 10 outputs, means connecting the decade to the output of the master oscillator to divide the continuously generated oscillator pulses into a continuous sequence of trains of 10 pulses which appear on the 10 counter outputs thereof respectively with each train of 10 pulses being separated from the next train of 10 pulses by a register shift pulse, a shift pulse output on said decade, means connecting the decade outputs to the input register and the accumulator register; a timer circuit having a number of outputs for count states equal to the number of digit stages in the input register and the accumulator register, the input of the timer circuit being connected to the output of the 10th pulse of the trains of 10 pulses from the input decade so that the 10th pulse causes the count states to equal the number of digit stages in the input register and the accumulator register, an invertor circuit connected to one of the count state outputs, a further invertor circuit connected to another of the count state outputs energized after the one count state; a function counter circuit having four outputs, means inverting a first output means connecting a second output to the register clearing means and a third output and a fourth output respectively to the adding means and the entering means; a slip counter circuit providing an inverted one count state output; a first set of gates connected to the input of the slip counter circuit, the first gate of the first set of gates having inputs connected to the first output of the function counter circuit, a first output of the timer circuit, the inverted one count state output of the slip counter circuit and the line of the enter function key switch respectively and a second gate of the first set of gates having inputs connected to the third output of the function counter circuit and the output of the 10th pulse from the input decade respectively; a first bistable circuit; a further gate circuit with an output connected to the input of the first bistable circuit and whose inputs are connected to the first output of the function counter circuit, the output of the other operating condition of the 10th pulse from the input decade and one of the outputs of the first bistable circuit respectively; a second bistable circuit; a still further gate circuit with an output connected to the input of the first bistable circuit and inputs connected to the first output of the function counter circuit, the third output of the timer circuit, one of the outputs of the second bistable, the output of the first pulse from the input decade and the inverted output of the other operating condition of the enter key switch respectively; a third bistable circuit and a third further gate circuit with an output connected to the input of the third bistable circuit and inputs connected to the first output of the function counter circuit, the output of the 10th pulse from the input decade, one of the outputs of the third bistable circuit and the output of the operating condition of the enter function key switch respectively; a second set of gates with an output connected to the input of the function counter circuit, the second set of gates including a first gate having inputs connected to the first output of the timer circuit, the output of the first pulse from the input decade counter, the inverted first output of the function counter circuit and the inverted output of the other operating condition of the enter key switch respectively, a second gate including a time delay having inputs connected to the first output of the function counter circuit, the output of the 10th pulse from the input decade, a second output of the timer circuit, the other output of the second bistable circuit the output of the other operating condition of the enter function key switch and the output of the time delay circuit respectively, a third gate having inputs connected to the second output of the function counter circuit, the second output of the timer circuit and the output of the 10th pulse from the input decade respectively and a fourth gate having inputs connected to the third output of the function counter circuit, the first output of the timer circuit, the output of the 10th pulse from the input decade and the output of other operating condition of the enter function switch respectively; said circuits connected in combination so that when the enter function key switch is depressed into the other operating condition so that the output thereof is energized, the second set of gates are energized to cause the first, second, third and fourth outputs of the function counter to be energized in turn to control the operation of the register clearing means, the adding means and the entry means; the first and second and third gates are energized to energize the outputs of the first and second bistable circuits respectively so as to control the adding means and the entry means respectively and the first and second gates of the first set of gates respectively are energized to set the slip counter at the initial position and to control the subsequent operation of the slip counter respectively.

5. A calculating machine according to claim 1, wherein the input register and the accumulator register each include a shift register buffer connected thereto so as to form an endless loop for circulating the digits of the number stored in the register; and wherein the input register and the accumulator register each include a carry store including a first bistable circuit whose output is connected to the output of the respective shift register buffer which is energized when a digit of predetermined value if stored in the shift register buffer; whereby, when a digit not of the predetermined value is circulated into the shift register buffer, the one output of the carry store first bistable is energized; and whereby, when a digit of the predetermined value is circulated into the shift register buffer, the other output of the carry store first bistable circuit is energized.

6. A calculating machine according to claim with an authentic operation control circuit wherein the register clearing means includes a fourth bistable circuit having an output energized at the end of an arithmetic operation and another output energized at the end of a nonarithmetic operation; a function counter with a plurality of outputs, a carry store bistable circuit for each register, a third set of gates having the output connected to the input of the shift register buffer of the input register, the first gate of the third set of gates having inputs connected to the second output of the function counter, the output of the operating condition of the enter function key switch and the other output of the fourth bistable circuit respectively, the second gate of the third set of gates having inputs connected to the second output of the function counter, and an output of the carry store first bistable circuit of the accumulator register respectively; and a fourth set of gates having the output connected to the input of the shift register buffer of the accumulator register, the first gate of the fourth set of gates having inputs connected to the second output of the function counter, an output of the carry store first bistable circuit of the input register, the output of the operating condition of the enter function key switch and the other output of the fourth bistable circuit respectively; said circuits connected in combination to operate when the enter function key switch is moved into the operating condition at the end of an arithmetic operation, so that the second gate of the third set of gates clears the enter number from the input register; and when the enter function key switch is moved into the operating condition at the end of a nonarithmetic operation, the first gate of the third set of gates overrides the second set of gates to retain the number in the input register and the first gate of the third set of gates clears the number from the accumulator register.

7. A calculating machine according to claim 6 wherein the register clearing means includes a decimal counter for storing a count state proportional to the decimal point of the accumulator register; a fifth bistable circuit having the input thereof connected to an output of the decimal counter and having an output energized when the count in the decimal counter reaches or passes a predetermined count state and another output energized when the count in the decimal counter does not reach the predetermined count state; a fifth set of gates having the output connected to the decimal counter, the first gate of the fourth set of gates having inputs connected to the other output of the decimal counter, the output of the operating condition of the enter function key switch and the other output of the fourth bistable circuit respectively; said circuits connected in combination to operate when the enter function key switch is moved into the operating condition at the end of an arithmetic operation so that the count state of the decimal counter is not cleared and when the enter function key switch is moved into the operating position at the end of a nonarithmetic operation, the count state of the decimal counter is cleared.

8. A calculating machme according to claim 6 wherein the adding means includes a means for aligning the number in the input register and the number in the accumulator register so that corresponding denominations enter the respective shift register buffers at the same time; and wherein the adding means includes a means for adding the corresponding denominations together.

9. A calculating machine according to claim 7 wherein the sum entering means includes a storage means, a first means for clearing from a stage of the accumulator register a digit representative of the stored digit into a storage means by a first entering means, and a second means for clearing the stage in the input register at the position corresponding to the cleared stage of the accumulator register, and including a second means for entering a digit representative of the digit stored in the storage means to the cleared register stages of the accumulator register and the input register, all being connected together in an operational circuit so that when the control means is operated, a representative digit is entered into the storage and the corresponding stages in the input register are cleared, and then a digit representative of the digit stored in the storage means is entered into the cleared stages of the accumulator and input registers. 

1. A calculating machine having programmed operations including an input register and an accumulator register, each register having a plurality of digit stages, a means for clearing the input register, a means for clearing the accumulator register, clearing control means operable from the previous program operation for controlling the operation of a single one of the register clearing means, an enter function key switch for initiating the operation of the clearing means, a means for entering a number in the input register and a number in the accumulator register, means adding the number in the input register to the number in the accumulatOr register and a means for entering the sum number into both the input register and the accumulator register by means of the enter key switch so that the clearing control means controls the clearing of one of the registers selected according to the previous program operation, the number in the cleared register is added to the number in the noncleared register and the sum number is entered into both the input register and the accumulator register.
 2. A calculating machine according to claim 1, including means to enter the sum number in the accumulator register into the input register.
 3. A calculating machine according to claim 1 wherein the enter function key switch has means for establishing in one operating condition a signal at one voltage level along a line and for the other operating condition establishing a signal at another voltage level along the line; and wherein an inverter circuit is connected to the line to produce an inverted output.
 4. A calculating machine according to claim 3 having control means including a master oscillator; and input decade having 10 outputs, means connecting the decade to the output of the master oscillator to divide the continuously generated oscillator pulses into a continuous sequence of trains of 10 pulses which appear on the 10 counter outputs thereof respectively with each train of 10 pulses being separated from the next train of 10 pulses by a register shift pulse, a shift pulse output on said decade, means connecting the decade outputs to the input register and the accumulator register; a timer circuit having a number of outputs for count states equal to the number of digit stages in the input register and the accumulator register, the input of the timer circuit being connected to the output of the 10th pulse of the trains of 10 pulses from the input decade so that the 10th pulse causes the count states to equal the number of digit stages in the input register and the accumulator register, an invertor circuit connected to one of the count state outputs, a further invertor circuit connected to another of the count state outputs energized after the one count state; a function counter circuit having four outputs, means inverting a first output means connecting a second output to the register clearing means and a third output and a fourth output respectively to the adding means and the entering means; a slip counter circuit providing an inverted one count state output; a first set of gates connected to the input of the slip counter circuit, the first gate of the first set of gates having inputs connected to the first output of the function counter circuit, a first output of the timer circuit, the inverted one count state output of the slip counter circuit and the line of the enter function key switch respectively and a second gate of the first set of gates having inputs connected to the third output of the function counter circuit and the output of the 10th pulse from the input decade respectively; a first bistable circuit; a further gate circuit with an output connected to the input of the first bistable circuit and whose inputs are connected to the first output of the function counter circuit, the output of the other operating condition of the 10th pulse from the input decade and one of the outputs of the first bistable circuit respectively; a second bistable circuit; a still further gate circuit with an output connected to the input of the first bistable circuit and inputs connected to the first output of the function counter circuit, the third output of the timer circuit, one of the outputs of the second bistable, the output of the first pulse from the input decade and the inverted output of the other operating condition of the enter key switch respectively; a third bistable circuit and a third further gate circuit with an output connected to the input of the third bistable circuit and inputs connected to the first output of the function counter circuit, the output of the 10th pulse from the input decade, one of the outputs of the third bistable circuit and the output of the operating condition of the enter function key switch respectively; a second set of gates with an output connected to the input of the function counter circuit, the second set of gates including a first gate having inputs connected to the first output of the timer circuit, the output of the first pulse from the input decade counter, the inverted first output of the function counter circuit and the inverted output of the other operating condition of the enter key switch respectively, a second gate including a time delay having inputs connected to the first output of the function counter circuit, the output of the 10th pulse from the input decade, a second output of the timer circuit, the other output of the second bistable circuit the output of the other operating condition of the enter function key switch and the output of the time delay circuit respectively, a third gate having inputs connected to the second output of the function counter circuit, the second output of the timer circuit and the output of the 10th pulse from the input decade respectively and a fourth gate having inputs connected to the third output of the function counter circuit, the first output of the timer circuit, the output of the 10th pulse from the input decade and the output of other operating condition of the enter function switch respectively; said circuits connected in combination so that when the enter function key switch is depressed into the other operating condition so that the output thereof is energized, the second set of gates are energized to cause the first, second, third and fourth outputs of the function counter to be energized in turn to control the operation of the register clearing means, the adding means and the entry means; the first and second and third gates are energized to energize the outputs of the first and second bistable circuits respectively so as to control the adding means and the entry means respectively and the first and second gates of the first set of gates respectively are energized to set the slip counter at the initial position and to control the subsequent operation of the slip counter respectively.
 5. A calculating machine according to claim 1, wherein the input register and the accumulator register each include a shift register buffer connected thereto so as to form an endless loop for circulating the digits of the number stored in the register; and wherein the input register and the accumulator register each include a carry store including a first bistable circuit whose output is connected to the output of the respective shift register buffer which is energized when a digit of predetermined value if stored in the shift register buffer; whereby, when a digit not of the predetermined value is circulated into the shift register buffer, the one output of the carry store first bistable is energized; and whereby, when a digit of the predetermined value is circulated into the shift register buffer, the other output of the carry store first bistable circuit is energized.
 6. A calculating machine according to claim 5 with an authentic operation control circuit wherein the register clearing means includes a fourth bistable circuit having an output energized at the end of an arithmetic operation and another output energized at the end of a nonarithmetic operation; a function counter with a plurality of outputs, a carry store bistable circuit for each register, a third set of gates having the output connected to the input of the shift register buffer of the input register, the first gate of the third set of gates having inputs connected to the second output of the function counter, the output of the operating condition of the enter function key switch and the other output of the fourth bistable circuit respectively, the second gate of the third set of gates having inputs connected to the second output of the functiOn counter, and an output of the carry store first bistable circuit of the accumulator register respectively; and a fourth set of gates having the output connected to the input of the shift register buffer of the accumulator register, the first gate of the fourth set of gates having inputs connected to the second output of the function counter, an output of the carry store first bistable circuit of the input register, the output of the operating condition of the enter function key switch and the other output of the fourth bistable circuit respectively; said circuits connected in combination to operate when the enter function key switch is moved into the operating condition at the end of an arithmetic operation, so that the second gate of the third set of gates clears the enter number from the input register; and when the enter function key switch is moved into the operating condition at the end of a nonarithmetic operation, the first gate of the third set of gates overrides the second set of gates to retain the number in the input register and the first gate of the third set of gates clears the number from the accumulator register.
 7. A calculating machine according to claim 6 wherein the register clearing means includes a decimal counter for storing a count state proportional to the decimal point of the accumulator register; a fifth bistable circuit having the input thereof connected to an output of the decimal counter and having an output energized when the count in the decimal counter reaches or passes a predetermined count state and another output energized when the count in the decimal counter does not reach the predetermined count state; a fifth set of gates having the output connected to the decimal counter, the first gate of the fourth set of gates having inputs connected to the other output of the decimal counter, the output of the operating condition of the enter function key switch and the other output of the fourth bistable circuit respectively; said circuits connected in combination to operate when the enter function key switch is moved into the operating condition at the end of an arithmetic operation so that the count state of the decimal counter is not cleared and when the enter function key switch is moved into the operating position at the end of a nonarithmetic operation, the count state of the decimal counter is cleared.
 8. A calculating machine according to claim 6 wherein the adding means includes a means for aligning the number in the input register and the number in the accumulator register so that corresponding denominations enter the respective shift register buffers at the same time; and wherein the adding means includes a means for adding the corresponding denominations together.
 9. A calculating machine according to claim 7 wherein the sum entering means includes a storage means, a first means for clearing from a stage of the accumulator register a digit representative of the stored digit into a storage means by a first entering means, and a second means for clearing the stage in the input register at the position corresponding to the cleared stage of the accumulator register, and including a second means for entering a digit representative of the digit stored in the storage means to the cleared register stages of the accumulator register and the input register, all being connected together in an operational circuit so that when the control means is operated, a representative digit is entered into the storage and the corresponding stages in the input register are cleared, and then a digit representative of the digit stored in the storage means is entered into the cleared stages of the accumulator and input registers. 